1. Field of the Invention
This invention relates to a flash memory device, in particular to a flash memory device that can program multi bits.
2. Description of a Related Prior Art
Generally, a flash memory device has both functions of electrical program and erasure. The flash memory device comprises a memory cell array and a peripheral circuit. The memory cell array has a plurality of memory cells which are arranged in matrix form between a word line and a bit line. The peripheral circuit has a power supply circuit and a circuit related to input and output of a data.
Such a conventional flash memory device will be briefly explained with reference to FIG. 1 as follows.
A conventional flash memory device comprises a memory cell array 1 in which a plurality of memory cells are connected in matrix form between a word line and a bit line, a row decoder 2 to supply a bias voltage into a select gate electrode of a memory cell selected by a word line and a column decoder 3 to supply a bias voltage into a drain electrode of a memory cell selected by a bit line.
The memory cell is classified into a stacked gate type and a split gate type according to form of a gate electrode. A memory cell having a split gate type is shown in FIG.2.
Referring to FIG. 2, a gate electrode, in which a tunnel oxide layer 5, a floating gate 6, a dielectric layer 7 and a control gate 8 are stacked, is formed on a silicon substrate 4. A drain 9 is formed in the silicon substrate 4 under a side of the gate electrode. A select gate 11 is formed on the silicon substrate 4 including the gate electrode, the select gate 11 being electrically isolated from the silicon substrate 4 and the gate electrode by a select gate oxide layer 10. A source 12 is formed in the silicon substrate 4 under the select gate 11, in which the source 12 is spaced from the drain 9 in constant distance.
To program information on the memory cell, that is, to store an electron charge into the floating gate 6, a voltage of 13 volt is applied to the control gate 8, a voltage of 1.8 volt is applied to the select gate 11, a voltage of 5 volt is applied to the drain 9, and the source 12 and the silicon substrate 4 are grounded. Hence, a select channel is formed in the silicon substrate 4 under the select gate 11 by means of the voltage applied to the select gate 11, and a channel is also formed in the silicon substrate 4 under the floating gate 6 by means of the high voltage applied to the control gate 8. A drain current flow through the select channel and a high electric field is formed in the channel under the floating gate 6. Some of the electrons existing in the channel become hot electrons since the electrons obtain energy during passing the high electric field region. Some of the hot electrons are injected to the floating gate 6 through the tunnel oxide layer 5 due to the vertical electric field formed by the high voltage applied to the control gate 8. Hence, the threshold voltage V.sub.T of the flash memory cell is raised.
To program a memory cell of the flash memory device described above, a bias voltage is selectively applied to a drain under a high voltage is applied to a word line and a source is ground. To make the flash memory device be have multi-bits program functions, a data buffer should be connected to a column multiplexer so that a bias voltage is applied to each drain of memory cells of multi-bits. In this case, the drain is affected stress since unnecessary bias voltage is applied to each drain of residual cells except for some memory cells that are to be program in the memory cells existing in an identical column. In particular, in case of that the memory cells existing in an identical column are divided into a plurality of sectors, the drain stress is occurred as much as it that multiplies by cycling frequency and number of the sectors.